Title:
Assistant Professor
Division:
The Electronics and Computers Division
Office:
105, 1st floor, Physics Building
Address:
Dept. of Physics, University of Patras, 26504, Patras, Greece
Phone:
+30 2610 996796
Email:
bakalis@upatras.gr
Hours Availability:
Tuesday 11:00-13:00, Thursday 11:00-13:00
Courses

1st Semester
  • Computer Programming I
    • 7th Semester
  • Digital Electronics

    • Short Bio

    Dimitris Bakalis received the Diploma degree, the M.Sc. degree and the Ph.D. degree in Computer Engineering, all from the Department of Computer Engineering and Informatics at the University of Patras in Greece. He is currently an Assistant Professor in the Physics Department at the same university.

    Dr. Bakalis has authored or co-authored more than 50 scientific papers in refereed international journals and conferences. His main research interests include VLSI Design and Test, Digital System Design and Test, Embedded Systems, Computer Arithmetic, Low Power Design and Test.

    He serves as an invited reviewer in several well-known international scientific conferences and journals. He is a member of the IEEE and the Technical Chamber of Greece.

    Research Activities
    1. D. Bakalis, X. Kavousianos, H. T. Vergos, D. Nikolos and G. Alexiou, Low Power Built-In Self-Test Schemes for Array and Booth Multipliers, VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, Gordon and Breach Publishers, vol. 12, no. 3, pp. 431-448, 2001
    2. X. Kavousianos, D. Bakalis, D. Nikolos and S. Tragoudas, A new Built-In TPG for Random Pattern Resistant Faults, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 21, no. 7, pp. 859-866, 2002
    3. D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos and G. Alexiou, On the Design of Low Power BIST for Multipliers with Booth Encoding and Wallace Tree Summation, Journal of Systems Architecture (JSA), Elsevier Science, vol. 48, no. 4-5, pp. 125-135, 2002
    4. E. Kalligeros, X. Kavousianos, D. Bakalis and D. Nikolos, On-the-fly Reseeding: A New Reseeding Technique for test-per-clock BIST, Journal of Electronic Testing: Theory and Applications (JETTA), Kluwer Academic Publishers, vol. 18, no. 3, pp. 315-332, 2002
    5. D. Bakalis, K. D. Adaos, D. Lymperopoulos, M. Bellos, H. T. Vergos, G. Ph. Alexiou and D. Nikolos, A Core Generator for Arithmetic Cores and Testing Structures with a Network Interface, Journal of Systems Architecture (JSA), Elsevier Science, vol. 52, no. 1, pp. 1-12, 2006
    6. X. Kavousianos, D. Bakalis and D. Nikolos, Efficient Partial Scan Cell Gating for Low-Power Scan-Based Testing, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 14, no. 2, Article 28, pp. 1-15, 2009
    7. D. Bakalis and H. T. Vergos, Shifter Circuits for {2^n+1, 2^n, 2^n-1} RNS, Electronics Letters, IET, vol. 45, no. 1, pp. 27-29, 2009
    8. H. T. Vergos, D. Bakalis and C. Efstathiou, Fast Modulo 2^n+1 Multi-Operand Adders and Residue Generators, Integration, the VLSI Journal, Elsevier, vol. 43, no. 1, pp. 42-48, 2010
    9. H. T. Vergos and D. Bakalis, On Implementing Efficient Modulo 2^n+1 Arithmetic Components, Journal of Circuits, Systems and Computers, World Scientific Publishing, vol. 19, no. 5, pp. 911-930, 2010
    10. D. Bakalis, H. T. Vergos and A. Spyrou, Efficient modulo 2^n±1 Squarers, Integration, the VLSI Journal, Elsevier, vol. 44, no. 3, pp. 163-174, 2011
    11. E. Vassalos, D. Bakalis and H. T. Vergos, On the Design of Modulo 2^n±1 Subtractors and Adders/Subtractors, Circuits, Systems and Signal Processing, Springer, vol. 30, no. 6, pp. 1445-1461, 2011
    12. E. Vassalos, D. Bakalis and H. T. Vergos, SUT-RNS Forward and Reverse Converters, in N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner (eds.), VLSI 2010 Annual Symposium: Selected Papers (ISBN: 978-94-007-1488-5), Lecture Notes in Electrical Engineering, vol. 105, chapter 14, pp. 231-244, 2011
    13. Η. T. Vergos and D. Bakalis, Area-Time Efficient Multi-Modulus Adders and their Applications, Microprocessors and Microsystems, Elsevier, vol. 36, no. 5, pp. 409-419, 2012
    14. E. Vassalos and D. Bakalis, CDS-RNS-based Single Constant Multipliers, Journal of Signal Processing Systems, Springer, vol. 67, no. 3, pp. 255-268, 2012
    15. E. Vassalos and D. Bakalis, Efficient architectures for modulo 2^n-2 arithmetic units, International Journal of Electronics, Taylor & Francis, vol. 102, no. 12, 2062-2074, 2015
    16. H. T. Vergos, D. Bakalis and A. Anastasiou, Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators, Circuits, Systems and Signal Processing, Springer, vol. 34, no. 4, 1041-1056, 2015